1. Field of the Invention
The present invention relates to a process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling.
2. Description of the Related Art
As is known, integration of electronic devices in a single wafer of semiconductor material requires particular solutions in order to decrease the effects of electromagnetic coupling due to the capacitances and mutual parasitic inductances that may form between the regions in which the active and/or passive components and the substrate of the wafer are made. These capacitances and mutual parasitic inductances, in fact, alter the characteristics of the devices and lead to an increase in the overall power dissipation. In addition, the problem of electromagnetic coupling with the substrate is particularly significant in the case of pure passive components, i.e., of those components that are designed to have a behavior of an exclusively capacitive, inductive, or resistive type in a wide frequency band.
The solutions so far proposed envisage the use of dielectric passivation layers which separate the regions comprising the components from the substrate. However, the fabrication processes currently available present limits which, in practice, do not enable formation of dielectric layers having satisfactory characteristics of insulation.
One first solution, for example, lies in growing a thermal-oxide layer of a thickness of a few micron on a surface of the wafer. In this case, however, the time required for carrying out the oxidation step is extremely long, on account of the low diffusiveness of the reagents, and the process is too slow to be exploited at an industrial level. Alternatively, it has been proposed to use thick layers of deposited oxide, which can be made in slightly shorter times. However, the improvement that is obtained is not yet sufficient and, moreover, the dielectric characteristics of the deposited oxide are inferior to those of the thermal oxide.
According to a different solution, silicon-on-insulator (SOI) semiconductor wafers are used, namely wafers incorporating a layer of buried oxide which separates the substrate from a monocrystalline- or polycrystalline-silicon region in which the components are formed. SOI wafers first of all present the disadvantage of being very costly, in so far as their preparation requires the use of complex processes; in the second place, the buried-oxide layers of SOI wafers currently available are not sufficiently thick to guarantee adequate electromagnetic insulation between the substrate and the components.
A further solution involves the fabrication of dielectric layers made of polymeric material. In this way, it is possible to reach even very high thicknesses and ones that are sufficient for reducing electromagnetic coupling considerably. In addition, it is possible to make passive devices suspended over the substrate (the so-called “air-bridge” devices), with the aim, above all, of minimizing the parasitic couplings of a capacitive type. The fabrication of thick polymeric layers is, however, disadvantageous because it requires the use of technologies and processing steps that are not standard in the sector of micro-electronics. Also in this case, then, the production cost of the device is very high. In addition, air-bridge devices cannot be passivated, entail the use of cavity packagings and are far from easy to reproduce.
The problem of electromagnetic coupling, then, afflicts particularly the inductors, so much so that they are not normally integrated on semiconductor wafers. In fact, precisely on account of the electromagnetic coupling between the turns and the substrate, at present it is not possible to produce inductors with a high figure of merit. On the other hand, recourse to alternative solutions, such as the use of highly resistive substrates, the formation of cavities that underlie the inductors, or recourse to techniques of three-dimensional lithography has the drawbacks already described (non-standard technologies or technologies that are not compatible with the fabrication of integrated circuits, high costs, packaging, etc.).